DATAMATH CALCULATOR MUSEUM
Texas Instruments TI-Nspire+ (Engineering Validation Tests 2)
|Date of introduction:||(never)||Display technology:|| LCD dot matrix
|New price:||Display size:||240 * 320 pixels|
|Size:|| 7.9" x 3.9" x 0.85"
200 x 100 x 22 mm3
|Weight:||8.8 ounces, 250 grams||Serial No:||P3-EVT2 031|
|Batteries:||4*AAA||Date of manufacture:||mth 05 year 2006|
|AC-Adapter:||Origin of manufacture:||China (S)|
|Precision:||14||Integrated circuits:|| CPU: TI-OMAP NP31AZZG
Flash: SST 39VF400A, ST NAND256W3A
Display: Novatek NT7702H, 2*xxx
|Program steps:||20M Bytes, 16M Bytes Flash ROM||Courtesy of:||Joerg Woerner|
noticed rumors in the graphing calculator community about an upcoming product
from Texas Instruments around June 2006 and it was obvious that they not refer
to the PET Project. It took about 6 month and the
first images of the TI-Nspire CAS+ appeared in different forums on the Internet.
These prototypes of the later TI-Nspire CAS were
used in different field tests all over the world and some of them found their
way to eBay auctions.
We acquired the featured TI-Nspire+ "Product 3, EVT2, serial number 031" on an eBay auction in the United States and we were surprised to find a CAS Operating System installed on the unit. We are still positive - based on various date codes of the integrated circuits and the numbers on the printed circuit boards - that it is a very early non-CAS calculator of the Phoenix project.
A great find for the Datamath Calculator Museum, probably disappointing for the regular customer!
At first glance looks this TI-Nspire+ very similar to the final device, but we observe some differences with the TI-Nspire introduced in July 2007:
• The cursor control makes use of inner and outer keys
• The color scheme is completely different
• Some function keys have different positions
We know (as of September 1, 2018) five versions of the TI-Nspire+ / TI-Nspire (Product 3):
|Name||Milestone||Serial No||Date of manufacture|
|TI-Nspire+||Engineering Validation Tests 1||P3-EVT2-031||May 2006|
|TI-XXXXXXXXXXX||Design Validation Tests 1.2||P3-ASIC-DVT1.2 0318||February 2007|
|TI-Nspire||Design Validation Tests 2 Lot A||A-P3-DVT2.0-0003||March 2007|
|TI-Nspire||Design Validation Tests 2 Lot B||B-P3-DVT2.0-1466||April 2007|
|TI-Nspire||Mass Production||2011007371||May 2007|
Learn more about the Five Engineering Stages.
We assume that Texas Instruments manufactured more than 1000 samples of the TI-Nspire CAS+ for evaluation purposes. Field tests were reported from Germany, Switzerland and New Zealand. As a result of these extensive tests we learned 2 major changes in the design and concept of the calculator till its official introduction in July 2007 (Europe) and September 2007 (USA):
TI-Nspire with its snap-in
TI-84 Plus Keypad
was added to the TI-Nspire CAS
• The internal architecture was optimized with respect to manufacturing costs
and power consumption
early TI-Nspire+ prototype reveals an internal design somewhere between the
PLT-SHH1 prototype based on the sophisticated POMAP1509E and the ZEVIO architecture
of the final TI-Nspire. Learn more about the
Hardware Architecture of TI’s Graphing Calculators.
Processor: The OMAP™ processor of the TI-Nspire+ prototype is labeled TI-OMAP NP31AZZG. We assume that this tiny chip is actually a System-on-Chip based on the OMAP5912 architecture from Texas Instruments hosting a ARM9 32-bit RISC processor clocked at 78 MHz and a TMS320C55xx Digital Signal Processor core.
Memory: The TI-Nspire+ engineering build unit makes use of three (one located on the backside of the PCB) different memory chips:
• NAND Flash-ROM
The NOR Flash-ROM was invented by Toshiba in 1984 and found its way immediately as a replacement of the more expensive ROM (NRE mask costs) and EEPROM (device costs) memory. The NOR Flash-ROMs use an address and data bus to allow the random access to any memory location. Main disadvantages of the NOR Flash-ROM compared to the NAND Flash-ROM are the higher costs, larger housings and slower write speeds.
The disassembled TI-Nspire+ (Manufactured May 2006) makes use of one SST
39VF400A, manufactured by Silicon Storage Technology,
Inc. with a 256k*16 bits organization. Please keep in mind that even the TI-89
Titanium used 2M*16 bits Flash-ROM.
The NAND Flash-ROM architecture was introduced by Toshiba in 1989 and is based on pages of typically 512 to 2048 Bytes and blocks of typical 32 or 64 pages.
While programming is performed on a page basis, erasure can only be performed on a block basis. NAND Flash-ROMs requires bad block management to be performed by device driver software or hardware. Due to the missing address bus the NAND Flash-ROM chip doesn't allow random access to the individual memory positions and therefore it can't be used for program memory of a microprocessor. Typical use of the NAND Flash-ROM is file based mass-memory storage such as memory cards.
The disassembled TI-Nspire+ makes use of one ST NAND256W3A NAND Flash-ROM with 32M Bytes size compared with 8M Bytes CMOS NAND EEPROM located in the PLT-SHH1 prototype.
SDRAM is the abbreviation of synchronous dynamic random access memory and is used as program and data memory for microprocessor systems. Each bit of data in a SDRAM is stored in separate capacitor on the integrated circuit. Since these capacitors leak charge over time, the information eventually fades unless the capacitor charge is refreshed periodically.
Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows SDRAM to reach very high density at low cost. Since SDRAM loses its data when the power supply is removed, it is accompanied usually by a NOR Flash-ROM.
During power-up of the system the program content of the NOR Flash-ROM is simply copied into the SDRAM and executed from there. We assume that the TI-Nspire uses the SDRAM as workspace for user data but stores changes on them into the NAND Flash-ROM.
The disassembled TI-Nspire+ makes use of one Infinion HYB18L256160 SDRAM with 16M*16 bits size compared with 8M*16 bits SDRAM located in the PLT-SHH1 prototype.
Please notice that all three memory chips are almost identical with the parts located in the released TI-Nspire CAS with the April 2007 manufacturing date. The only difference is the supply voltage, it was lowered from 3.3 volts to 1.8 volts.
Display: The TI-Nspire
CAS+ uses a high-contrast display with a
resolution of 240 * 320 pixels, a huge improvement over the TI-89 Titanium with
100 * 160 pixels or the Voyage 200 with 128 * 240 pixels. The large 16-level
grey-scale display includes a novel split screen capability with up to 4 views.
The driver circuit of the LC-Display is compromised of 2 column driver and one row driver manufactured by Novatek, Taiwan. We located a NT7702H row driver as bare chip mounted on a flexible piece of circuit board attached between the display and a PCB and two unknown column drivers.
• TI-Nspire+ (Engineering Validation Tests P3-EVT2-031)
18.104.22.168.347T (May 10, 2006)
Serial Number: 39C10E26
You can check the ROM version of your TI-Nspire CAS+ using the following key sequence and reading the number on your screen:
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Information provided by Xavier Andréani.
Computer Link Software for Windows
Since the TI-Nspire+ lacks a QWERTY keyboard it is
permitted (as of September 27, 2007) for use on SAT,
PSAT and AP exams.
Calculators with computer algebra system (CAS) functionality are not allowed on
If you have additions to the above article please email: firstname.lastname@example.org.
© Joerg Woerner, August 26, 2018. No reprints without written permission.