Texas Instruments TI-Nspire CAS

Date of introduction:  July 2007 Display technology:  LCD dot matrix
 16-level greyscale
New price:  $159.00 (SRP 2008) Display size:  240 * 320 pixels 
Size:  7.9" x 3.9" x 0.85"
 200 x 100 x 22 mm3
Weight:  8.9 ounces, 252 grams Serial No:  2016002483
Batteries:  4*AAA Date of manufacture:  mth 04 year 2007
AC-Adapter:   Origin of manufacture:  China (S)
Precision:  14 Integrated circuits:  CPU: TI-NS2006A-1 (L9A0654)
 SDRAM: HYB18L256160
 Flash: SST 39WF400A, ST NAND256R3A
 Display: Novatek NT7702H, 2*xxx
Program steps:  20M Bytes, 16M Bytes Flash ROM Courtesy of:  Joerg Woerner 

In Germany is a saying "Good things take time", we assume in Dallas it is "and better things even longer". But the long-awaited TI-Nspire™ arrived finally in the store shelves and it was worth waiting for! Don't miss the original Phoenix 1 and three different prototypes of the TI-Nspire CAS+ labeled EVT2, DVT1 and PVT1.1 - learn more about the Five Engineering Stages. The latter seems to be close to the TI-nspire™ CAS+ introduced May 12, 2006 in New Zealand.

PLT-SHH1_EP.jpg (145829 Byte)Texas Instruments filed already October 24, 2003 in Europe a patent application for a stylus based calculator and since the publication of the granted patent EP1424626 in June 2004 there are rumors about a new graphing calculator. The patent itself describes a then novel method of entering data with a stylus into graphing software applications. The sketch of the suggested design of the new calculator reminds us immediately to a failed development project nicknamed PET by the marketing department of Texas Instruments. We discovered in 2007 one of the rare prototypes labeled TI-PLT.

The TI-Nspire CAS obviously lacks a stylus and seems to trace back to another root than the “PDA-based graphing calculator”, a hype started early in this millennium with the Hewlett Packard Xpander. This Windows CE based calculator looked like a PDA with a 240 * 320 pixel gray-scale touch screen, a small numeric keypad and the stylus. Hewlett Packard cancelled the project February 2001 with just a few prototypes left to the disappointed market. Dismantling one of the prototypes revealed a design centered around a Hitachi SH3 RISC-Processor, 8M Bytes of SDRAM and 16M Bytes of ROM.  

Japanese calculator company Casio was more successful and introduced in 2002 the ClassPad 300 with a 160 * 240 pixel gray-scale touch screen supporting a lot of stylus based operation like drag-and-drop. This design makes use of the Hitachi SH7291 - a SH3 based RISC-Processor, 0.5M Bytes of RAM and 4M Bytes Flash-ROM. 

The ClassPad 300 Plus introduced in 2005 makes use of a much improved display with higher contrast and better readability under low lighting conditions.

The TI-Nspire CAS is not just a calculator, it is a complete family of products based on:

The TI-Nspire handheld, priced comparably to the TI-84 Plus Silver Edition and
    delivered with a snap-in TI-84 Plus Keypad
The TI-Nspire CAS (Computer Algebra System) handheld, priced comparably 
    to the TI-89 Titanium
The TI-Nspire computer software with the same capabilities as the TI-Nspire
    and TI-Nspire CAS handheld

TI-NspireCAS_Bat.jpg (117382 Byte)TI-NspireCAS_Back.jpg (100113 Byte)At first glance the TI-Nspire CAS looks like the successor of the TI-89 Titanium and Voyage 200 calculators, actually a design based on technology from 1998 (TI-89). Nevertheless states the TI-Nspire CAS website in May 2007 clearly in the FAQ's:

Is TI-Nspire CAS technology meant to replace the TI-89 Titanium graphing calculator or Voyage™ 200 personal learning tool?

No. The TI-89 Titanium graphing calculator and Voyage 200 personal learning tool will continue to be offered and supported by TI. Because the TI-Nspire CAS handheld and computer software combine new TI-Nspire features with Computer Algebra System capabilities built in, they offer educators an added option to incorporate CAS into their lessons.

Don't miss the impressive ViewScreen panel for the TI-Nspire family.

The TI-Nspire Lab Cradle requires the new Operating System 3.0 (introduced in May 2011) or higher.

Architecture: TI-NspireCAS_PCB1.jpg (321554 Byte)TI-NspireCAS_PCB.jpg (522912 Byte)Dismantling the TI-Nspire CAS reveals a modern architecture based on the ZEVIO architecture introduced by LSI Logic early in 2006. The ZEVIO architecture is ideally suited for consumer electronics products such as GPS navigation systems, electronic toys and edutainment applications, personal media players, and handheld products. The System-on-Chip (SoC) approach of the ZEVIO is centered around Intellectual Property blocks from ARM (e.g. the 90 MHz ARM9 32-bit RISC processor), LSI Logic's 200-MHz 16-bit ZSP-400 Digital Signal Processor, 16-bit SDRAM memory controller, NAND flash memory controller, USB-2.0 (including USB On the Go), IEEE 1394 Firewire, and Secure Digital I/O and a LCD controller for TFT displays. We noticed this approach already with the PLT-SHH1 prototype based on the sophisticated POMAP1509E, a design based on the OMAP™1510 series dual-core processor. Learn more about the Hardware Architecture of TI’s Graphing Calculators.

TI-NspireCAS_SOC.jpg (410059 Byte)Processor: The current (April 2007) chips with the TI-NS2006A-1 / L9A0654 identification are designed in a 0.13um process and manufactured in any of LSI Logic's foundries, which include Semiconductor Manufacturing International, Taiwan Semiconductor Manufacturing and United Microelectronics.

TI-NspireCAS_Memoryx.jpg (143964 Byte)Memory: The TI-Nspire CAS makes use of three different memory chips:


Flash memory is non-volatile and does not need a battery to maintain the information stored in the chip. In the past years two different technologies emerged in parallel with some advantages and disadvantages.

The NOR Flash-ROM was invented by Toshiba in 1984 and found its way immediately as a replacement of the more expensive ROM (NRE mask costs) and EEPROM (device costs) memory. The NOR Flash-ROMs use an address and data bus to allow the random access to any memory location. Main disadvantages of the NOR Flash-ROM compared to the NAND Flash-ROM are the higher costs, larger housings and slower write speeds.

The disassembled TI-Nspire CAS (Manufactured April 2007) makes use of one SST 39WF400A, manufactured by Silicon Storage Technology, Inc. with a 256kx16 bits organization. Please keep in mind that even the TI-89 Titanium used 2Mx16 bits Flash-ROM.

The NAND Flash-ROM architecture was introduced by Toshiba in 1989 and is based on pages of typically 512 to 2048 Bytes and blocks of typical 32 or 64 pages.

While programming is performed on a page basis, erasure can only be performed on a block basis. NAND Flash-ROMs requires bad block management to be performed by device driver software or hardware. Due to the missing address bus the NAND Flash-ROM chip doesn't allow random access to the individual memory positions and therefore it can't be used for program memory of a microprocessor. Typical use of the NAND Flash-ROM memory is file based mass-memory storage such as memory cards.

The disassembled TI-Nspire CAS makes use of one ST NAND256R3A NAND Flash-ROM chip with 32M Bytes capacity compared with 8M Bytes CMOS NAND EEPROM located in the PLT-SHH1 prototype.

SDRAM is the abbreviation of synchronous dynamic random access memory and is used as program and data memory for microprocessor systems. Each bit of data in a SDRAM is stored in separate capacitor on the integrated circuit. Since these capacitors leak charge over time, the information eventually fades unless the capacitor charge is refreshed periodically.

Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows SDRAM to reach very high density at low cost. Since SDRAM loses its data when the power supply is removed, it is accompanied usually by a NOR-Flash memory.

During power-up of the system the program content of the NOR-Flash is simply copied into the SDRAM and executed from there. We assume that the TI-Nspire uses the SDRAM as workspace for user data but stores changes on them into the NAND-Flash memory.

The disassembled TI-Nspire CAS makes use of one Qimonda HYB18L256160 SDRAM chip with 16Mx16 bits capacity compared with 8Mx16 bits SDRAM located in the PLT-SHH1 prototype.

TI-NspireCAS_2_Menue.jpg (161376 Byte)Display: The TI-Nspire CAS uses a high-contrast display with a resolution of 240 * 320 pixels, a huge improvement over the TI-89 Titanium with 100 * 160 pixels or the Voyage 200 with 128 * 240 pixels. The large 16-level greyscale displays includes a novel split screen capability with up to 4 views.

Texas Instruments announced on March 8, 2010 the new TI-Nspire CAS Touchpad and Operating System 2.0. The new OS 2.0 was released for this TI-Nspire CAS with Clickpad, too.


TI-Nspire CAS

TI-NspireCAS_V11_OS.jpg (88858 Byte)1.1.9170 (May 07, 2007)  
Boot1 Code Version: 1.1.8916
Boot2 Code Version: 1.1.8981

1.2.2394 (August 30, 2007)

TI-NspireCAS_S0407_V13_OS.jpg (85608 Byte)1.3.2437 (January 8, 2008)

1.4.11643 (July 9, 2008)
Boot1 Code Version: 1.1.8916
Boot2 Code Version: 1.4.1571

TI-NspireCAS_S0407_V16_OS.jpg (88616 Byte)1.6.4295 (October 29, 2008, released December 9, 2008)

1.7.2741 (May 19, 2009, released June 6, 2009) (March 5, 2010) (May 3, 2010) (July 17, 2010) (April 2011) (May 2011)  

You can check the ROM version of your TI-Nspire CAS using the following key sequence and reading the number on your screen:

[HOME] [8] [4] (1.1 ... 1.6) OR
[HOME] [8] [5] (1.7) OR
[HOME] [5] [4] (2.0 ... 3.0)

Information provided by Xavier Andréani.

TI-Nspire Computer Link Software for Windows


1.2.2412 (December 21, 2007)

1.3.2439 (Trial: January 8, 2008)

1.4.11654 (July 8, 2008)

Exam acceptance:

Since the TI-Nspire CAS lacks a QWERTY keyboard it is permitted (as of September 27, 2007) for use on SAT, PSAT and AP exams. Calculators with computer algebra system (CAS) functionality are not allowed on ACT exams.

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If you have additions to the above article please email:

© Joerg Woerner, July 24, 2007. No reprints without written permission.