DATAMATH CALCULATOR MUSEUM |
In the New Product Development process are typically five Engineering Stages (without product support) defined:
1. Conception
2. Feasibility
3. Product
development
4. Pilot production
5. Full commercialization
With
respect to the hardware (printed circuit boards – PCBs) of a completely new
calculator like the TI-Nspire CAS you would expect five different "qualities" of the
builds:
• Stage 3: Prototype
(PROTO)
• Stage 3: Engineering Validation Test
(EVT)
• Stage 3: Design Validation Test (DVT)
•
Stage 4: Production Validation Test (PVT)
• Stage
5: Mass Production (MP)
Texas Instruments did us a great favor and used these abbreviations on the PCBs of the various Phoenix 1, TI-Nspire CAS+, TI-Nspire CAS and TI-Nspire calculators both Xavier Andréani and I acquired over the years for the Datamath Calculator Museum. Breaking this code and understanding the date codes on the PCBs, we can reconstruct the timeline of the TI-Nspire development and discover some new insights.
2006 - The Phoenix 1 / TI-Nspire CAS+ - Another canceled project?
Reconstruction of the timeline should rely on the date codes, not the software version of the calculators. We found "old builds" with updated software looking more recent from the outside than "new builds" with still the original software.
Phoenix 1 / TI-Nspire CAS+ (Product 1) | |||||
BUILD | Serial
Number Product Name |
SW-Version Date (mm/dd/year) |
Main-PCB Date (wk/yr) |
LCD-PCB Date code (wk/yr) |
CPU/ASIC Date code (wk/yr) |
Stage 3,
Feb. 2006 EVT Built 1 |
P1-EVT1-B-0118 Phoenix 1 |
none 02/15/2006 |
PH1_EVT2_MB_6412 03/2006 |
PH1_EVT1_LCDB_2412 51/2005 |
OMAP NP31AZZG TBD |
Stage 3,
Apr. 2006 EVT Built 2 |
P1-EVT2-0135 None |
1.0.1.0.334T 05/01/2006 |
PH1_EVT2_MB_6413 06/2006 |
PH1_EVT2_LCDB_2413 09/2006 |
OMAP NP31AZZG TBD |
Stage 3,
Jun. 2006 DVT Built 1 |
P1-DVT1-000150 None |
1.0.494 07/27/2006 |
PH1_DVT1_MB_6421 13/2006 |
PH1_DVT1_LCDB_2421 13/2006 |
OMAP NP31AZZG TBD |
Stage 4,
Aug. 2006 PVT Built 1 |
P1-PVT1-000180 TI-nspire CAS+ |
TBD TBD |
PH1_PVT_MB_6430 31/2006 |
PH1_PVT_LCDB_2430 31/2006 |
OMAP NP31AZZG TBD |
Stage 4.5,
Oct. 2006 Ramp up |
P1-PVT1.1-02768 TI-nspire CAS+ |
1.0.554 08/28/2006 |
PH1_MP_MB_6441 37/2006 |
PH1_PVT_LCDB_2430 39/2006 |
OMAP NP31AZZG TBD |
Please notice that the mainboard of the TI-Nspire CAS+ with the serial number PVT1.1 02768 is labeled PH1_MP_MB_6441. MP for Mass Production, but it never made it into the shelves of your local dealer!
FYI: The hundreds of TI-Nspire CAS+ calculators
you find on eBay since 2007 are usually from this built.
2006 and 2007 - The TI-Nspire CAS
and the new non-CAS version plus TI-84 Plus emulation.
With the TI-Nspire CAS+ out in the field for various tests with teachers and students since 2006, it took quite a while till the official introduction of the TI-Nspire Family in July 2007 (Europe) respectively September 2007 (United States). What happened? We are not completely sure after the inspection of seven different TI-Nspire CAS and non-CAS "Pre-production" and multiple "Production" samples.
TI-Nspire CAS (Product 1, Revision 2) | |||||
BUILD | Serial
Number Product Name |
SW-Version Date (mm/dd/year) |
Main-PCB Date (wk/yr) |
LCD-PCB Date code (wk/yr) |
CPU/ASIC Date code (wk/yr) |
Stage 3,
Jan. 2007 Revision 2, DVT Built 1.2 |
P1R2-DVT1.2-620 TI-XXXXXXXXXXX |
1.1.8099 03/25/2007 |
P1R2_DVT1.2_MB_6422 02/2007 |
P3_LB_DVT1.2_2425 03/2007 |
L9A0654
NS2006A 39/2006 |
Stage 3,
Jan. 2007 Revision 2, DVT Built 1.2 |
P1R2-DVT1.2-682 TI-XXXXXXXXXXX |
1.2.2344 08/22/2007 |
P1R2_DVT1.2_MB_6422 02/2007 |
P3_LB_DVT1.2_2425 03/2007 |
L9A0654
NS2006A 39/2006 |
Stage 3,
Feb. 2007 Revision 2, DVT Built 2.0 |
P1R2-DVT2.0-0105 TI-nspire CAS |
1.2.2344 08/22/2007 |
P1R2_DVT2_MB_6423 07/2007 |
P3_LB_DVT2_2426 TBD |
L9A0654
NS2006A 45/2006 |
Stage 3,
Mar. 2007 Revision 2, DVT Built 2.0 |
P1R2-DVT2.0-3069 TI-nspire CAS |
1.1.8408 04/04/2007 |
P1R2_DVT2_MB_6423 09/2007 |
P3_LB_DVT2_2426 TBD |
L9A0654
NS2006A 04/2007 |
Stage 5,
Apr. 2007 Mass Production |
2016002483 TI-nspire CAS |
1.1.9170 05/07/2007 |
P1R2_MP_MB_6440 13/2007 |
P1R2/P3_LB_MP_2440 TBD |
L9A0654
NS2006A-1 05/2007 |
TI-Nspire non-CAS (Product 3) | |||||
BUILD | Serial
Number Product Name |
SW-Version Date (mm/dd/year) |
Main-PCB Date (wk/yr) |
LCD-PCB Date code (wk/yr) |
CPU/ASIC Date code (wk/yr) |
Stage 3,
May 2006 EVT Built 2 |
P3-EVT2-031 TI-nspire+ |
1.0.1.0.347T (CAS) 05/10/2006 |
P2/P3 OMAP MB_6411 18/2006 |
TG2983LB-2411-060515 21/2006 |
OMAP NP31AZZG TBD |
Stage 3,
Feb. 2007 DVT Built 1.2 |
P3-ASIC-DVT1.2 0318 TI-XXXXXXXXXXX |
1.1.9227 05/15/2007 |
P2/P3 ASIC MB_DVT1.2_6423 03/2007 |
P3_LB_DVT1.2_2425 03/2007 |
L9A0654
NS2006A 35/2006 |
Stage 3,
Feb. 2007 DVT Built 1.2 |
P3-ASIC-DVT1.2 0999 TI-XXXXXXXXXXX |
1.1.7320 02/26/2007 |
P2/P3 ASIC MB_DVT1.2_6423 03/2007 |
P3_LB_DVT1.2_2425 03/2007 |
L9A0654
NS2006A 35/2006 |
Stage 3,
Mar. 2007 DVT Built 2.0 - Lot A |
A-P3-DVT2.0-0003 TI-nspire |
1.1.8008 03/22/2007 |
P2/P3 ASIC MB_DVT2_6424 06/2007 |
P3_LB_DVT2_2426 TBD |
L9A0654
NS2006A 39/2006 |
Stage 3,
Apr. 2007 DVT Built 2.0 - Lot B |
B-P3-DVT2.0-1466 TI-nspire |
1.1.8410 04/15/2007 |
P2/P3 ASIC MB_DVT2_6424 10/2007 |
P3_LB_DVT2_2426 TBD |
L9A0654
NS2006A 45/2006 |
Stage 5,
May 2007 Mass Production |
2011007371 TI-nspire |
1.1.9170 05/07/2007 |
P1R2_MP_MB_6440 16/2007 |
P1R2/P3_LB_MP_2440 TBD |
L9A0702
NS2006A-0 14/2007 |
Everything fits easily into a timeline – even
the introduction of the TI-Nspire Family in Summer / Fall 2007. Please remember,
the TI-Nspire is software, software, and software.
Everything? Not really, we discovered a major switch in the hardware between the OMAP-based TI-Nspire CAS+ and the ASIC-based TI-Nspire CAS / non-CAS calculators.
With the earliest ASIC we located so far manufactured in
August 2006 and a production ready TI-Nspire CAS+ manufactured in October 2006
we still don’t know for sure what happened to the TI-Nspire CAS+. We guess the
Phoenix failed!
If you have additions to the above article please email: joerg@datamath.org.
© Joerg Woerner and Xavier Andréani, January 5, 2012. Major update on August 31, 2018. No reprints without written permission.