DATAMATH CALCULATOR MUSEUM
Texas Instruments Personal Learning Tool PLT FHH1
|Date of introduction:||never||Display technology:||LCD dot matrix|
|New price:||Display size:||480 * 320 pixels|
|Size:|| 5.0" x 8.5" x 1.2"
126 x 215 x 31 mm³
|Weight:||19.2 ounces, 546 grams||Serial No:|
|Batteries:||Li-Ion 3.7V 1400mAh||Date of manufacture:||year 2002|
|AC-Adapter:||Origin of manufacture:||Taiwan (I)|
|Precision:||Integrated circuits:|| CPU: TI-OMAP1509E
SDRAM: Hynix HY57V281620A
Flash: Toshiba TC58128A, Fujitsu 29LV400TC
|Program steps:||16M Bytes SDRAM, 512k Bytes NOR Flash ROM, 16M Bytes NAND Flash ROM||Courtesy of:||Texas Instruments|
Datamath Calculator Museum received this unique graphing calculator as a loan from Texas Instruments in
February 2008 to photograph and document it.
We assume that only about 500 prototypes of
the PLT FHH1 were used for field tests but none showed up on eBay till now.
Comparing the PLT FHH1 with the PLT SHH1
reveals an important difference: While the smaller SHH1 still features a
traditional keyboard for easy operation, hosts the larger FHH1 just 8 keys and
the cursor control. Similar to a modern PDA (Personal Digital Assistant) is the
calculator operated by a Stylus. We assume that a keyboard was developed as an
optional, external input device.
The Li-ion battery of the PLT FHH1 states three different products to be powered with:
PLT SHH1: Spot Hand Held
Dismantling the PLT FHH1
reveals a modern architecture based on the OMAP architecture introduced by Texas
Instruments already in 2001. Learn more about the
Hardware Architecture of TIs Graphing Calculators. The different memory chips used in this Engineering
Samples promised an unbelievable huge workspace of 32M Bytes and even an
additional slot for a SD Memory Card. In addition we recognized an unknown
Philips CA4885 device.
memory is non-volatile and does not need a battery to maintain the information
stored in the chip. In the past years two different technologies emerged in
parallel with some advantages and disadvantages.
The NOR Flash-ROM was invented by Toshiba in 1984 and found its way immediately as a replacement of the more expensive ROM (NRE mask costs) and EEPROM (device costs) memory. The NOR Flash-ROMs use an address and data bus to allow the random access to any memory location. Main disadvantages of the NOR Flash-ROM compared to the NAND Flash-ROM are the higher costs, larger housings and slower write speeds.
disassembled PLT FHH1 (Manufactured 2002) makes use of one 29LV400TC,
manufactured by Fujitsu, Japan with a 256k*16
bits organization. Please keep in mind that even the
used 2M*16 bits Flash-ROM.
NAND Flash-ROM architecture was introduced
by Toshiba in 1989 and is based on pages of typically 512 to 2048 Bytes and
blocks of typical 32 or 64 pages.
programming is performed on a page basis, erasure can only be performed on a
block basis. NAND Flash-ROMs requires bad block management to be performed by
device driver software or hardware. Due to the missing address bus the NAND
Flash-ROM chip doesn't allow random access to the individual memory positions
and therefore it can't be used for program memory of a microprocessor. Typical
use of the NAND Flash-ROM memory is file based mass-memory storage such as
disassembled PLT FHH1 makes use of one Toshiba TC58128A NAND
EEPROM with 16M
Bytes size compared with 32M Bytes CMOS NAND Flash-ROM located in the later TI-Nspire.
is the abbreviation of synchronous dynamic random access memory and is used as
program and data memory for microprocessor systems. Each bit of data in a SDRAM
is stored in separate capacitor on the integrated circuit. Since these
capacitors leak charge over time, the information eventually fades unless the capacitor
charge is refreshed periodically.
of this refresh requirement, it is a dynamic memory as opposed to SRAM and other
static memory. Its advantage over SRAM is its structural simplicity: only one
transistor and a capacitor are required per bit, compared to six transistors in
SRAM. This allows SDRAM to reach very high density at low cost. Since SDRAM
loses its data when the power supply is removed, it is accompanied usually by a
NOR Flash memory.
power-up of the system the program content of the NOR Flash-ROM is simply copied
into the SDRAM and executed from there. We assume that the PLT FHH1 uses the
SDRAM as workspace for user data but stores changes on them into the NAND Flash-ROM.
disassembled PLT FHH1 makes use of one Hynix HY57V281620A SDRAM with 8M*16 bits
compared with 16M*16 bits SDRAM located in the later TI-Nspire.
The PLT FHH1 uses a high-contrast display with a resolution of 480 * 320 pixels,
a huge improvement over the TI-89 Titanium with 100 * 160 pixels or the Voyage
200 with 128 * 240 pixels. The large touch-screen display includes a novel split
screen capability with up to 4 views.
Serial port similar
Connector for Charging cradle
USB 1.1 connector
serial port of the calculator allows the connection to the Calculator-Based
Laboratory system CBL 2
and the Calculator-Based Ranger CBR
and probably an external keyboard.
Instruments worked secretly on the
Phoenix 1 and announced in 2006 the TI-Nspire CAS+, but it took another year before the
calculator family arrived finally July 2007 in the store shelves.
If you have additions to the above article please email: email@example.com.
© Joerg Woerner, March 6, 2008. No reprints without written permission.