DATAMATH CALCULATOR MUSEUM
Texas Instruments TI-Nspire CX II CAS
|Date of introduction:||March 6, 2019||Display technology:|| LCD dot matrix
16-bit color, backlit
|New price:||Display size:||240 * 320 pixels|
|Size:|| 7.5" x 3.4" x 0.60"
190 x 87 x 15 mm3
|Weight:||7.3 ounces, 206 grams||Serial No:||4935014492|
|Batteries:||3.7L1200SPA Li-Ion||Date of manufacture:||mth 04 year 2019 (AH)|
|AC-Adapter:||Origin of manufacture:||Malaysia (M)|
|Precision:||14||Integrated circuits:|| CPU: ET-NS2018-001 (S6M98)
SDRAM Micron MT46H32M
Flash-ROM: Micron MT29F1G01
|Program steps:||64M Bytes, 90M Bytes Flash ROM||Courtesy of:||Joerg Woerner|
Texas Instruments introduced at the 2011 T3 International Conference held on February 25-27 in San Antonio, TX with the TI-Nspire CX and TI-Nspire CX CAS their first graphing calculators with full color, backlit displays. Eight years later, on March 6, 2019, Texas Instruments released a very promising press release:
It's a big day for Texas Instruments. Today, we introduced the all-new TI-Nspire CX II family of graphing calculators, bringing a 2 ½ times faster processor, an updated, new look and added math and coding features that will help bring STEM (science, technology, engineering and math) subjects to life for students. Building on the popular TI-Nspire CX line of graphing calculators, the new TI-Nspire CX II and TI-Nspire CX II CAS give students more opportunities to visualize important, abstract concepts, not just in math class, but in science and computer programming courses.
this TI-Nspire CX II CAS with the Date code M-0419AH manufactured in
April 2019 in Malaysia
by Inventec reveals a very
compact design based on just one (not counting the small Trackpad) printed circuit board (PCB) with just a
few main Integrated Circuits. The design reminds us about TI-Nspire design
NSC CR IV
(Cost Reduction Phase IV) but dropped the Multichip Package of the Memory in
favor of two discrete chips for NAND
Flash ROM and SDRAM.
Processor: The ARM9 CPU is integrated into an ASIC with the markings ET-NS2018-001 (S6M98), we couldn't identify its manufacturer as of today. The ARM9 core is clocked with 396 MHz compared to the 156 MHz of the previous TI-Nspire CX or 132 MHz of the original TI-Nspire CX. Learn more about the Hardware Architecture of TIs Graphing Calculators.
The -001 marking of the ASIC is unique to the TI-Nspire CX II CAS, the other family members vary in the code:
TI-Nspire CX II,
CX II EZ-Spot
001: TI-Nspire CX II CAS, TI-Nspire CX II-T CAS, TI-Nspire CX II-C CAS
100: TI-Nspire CX II-T
Memory: The TI-Nspire CX II CAS makes use of three different memory technologies:
Flash memory is non-volatile and does not need a battery to maintain the information stored in the chip. In the past years two different technologies emerged in parallel with some advantages and disadvantages.
The NOR Flash-ROM was invented by Toshiba in 1984 and found its way immediately as a replacement of the more expensive ROM (NRE mask costs) and EEPROM (device costs) memory. NOR Flash-ROMs use an address and data bus to allow the random access to any memory location. Main disadvantages of NOR Flash-ROMs compared to NAND Flash-ROMs are the higher costs, larger housings and slower write speeds.
The disassembled TI-Nspire CX II CAS manufactured in April 2019 lacks a NOR Flash-ROM chip, we assume that the ET-NS2018 ASIC integrates - like its predecessors - a a ROM with a capacity of 512k Bytes used for the first-stage bootloader ("Boot 1").
The NAND Flash-ROM architecture was introduced by Toshiba in 1989 and is based on pages of typically 512 to 2048 Bytes and blocks of typical 32 or 64 pages. While programming is performed on a page basis, erasure can only be performed on a block basis. NAND Flash-ROMs requires bad block management to be performed by device driver software or hardware. Due to the missing address bus the NAND Flash-ROM chip doesn't allow random access to the individual memory positions and therefore it can't be used for program memory of a microprocessor. Typical use of NAND Flash-ROM memory is file based mass-memory storage such as memory cards.
The disassembled TI-Nspire CX II CAS manufactured in April 2019 uses a Serial NAND Flash-ROM with a part designation Micron NW873. Using Micron's part number decoder expands the NW873 code to MT29F1G01ABBFDWB-IT and the Part Numbering System explains:
| Product Family 29F: Single-Supply NAND Flash-ROM
Density 1G: 1G Bits
Device Width 01: 1 bit (Serial)
Level A: SLC (Single Level Cell)
Classification B: Discrete, 1 Chip Select
Operating Voltage Range B: 1.8V
Generation Feature Set F: 6th Generation Die
Interface D: SPI
Package Code WB: 8-pin U-PDFN
Operating Temperature Range -IT: -40ºC to +85ºC
SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory and is used as program and data memory for microprocessor systems. Each bit of data in a SDRAM is stored in separate capacitor on the integrated circuit. Since these capacitors leak charge over time, the information eventually fades unless the capacitor charge is refreshed periodically.
Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM cells. This allows SDRAM to reach very high density at low cost. Since SDRAM loses its data when the power supply is removed, it is accompanied usually by a NOR Flash-ROM.
During power-up of the system the program content of the NOR Flash-ROM is with the integrated bootloader simply copied into the SDRAM and executed from there. We assume that the TI-Nspire CX II CAS uses the SDRAM as workspace for user data but stores changes on them into its NAND Flash-ROM.
The disassembled TI-Nspire CX II CAS manufactured in April 2019 uses a Mobile LPDDR with a part designation Micron D9LQQ. Using Micron's part number decoder expands the D9LQQ code to MT46H32M16LFBF-5 IT and the Part Numbering System explains:
| Product Family 46: Mobile LPDDR
Operating Voltage Range H: 1.8V
Configuration 32M16: 32M x 1G Bits
Addressing LF: JEDEC-standard
Package Code BF: 60-ball (8mm x 9mm) VFBG
Cycle Time -5: 5ns / 200 MHz
Operating Temperature Range -IT: -40ºC to +85ºC
TI-Nspire CX II CAS
126.96.36.1993 (March 22, 2019)
You can check the ROM version of your TI-Nspire CX II CAS using the following key sequence and reading the number on your screen:
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Information provided by Xavier Andrιani.
Since the TI-Nspire CX II CAS lacks a QWERTY keyboard it is permitted (as of May 30, 2013) for use on SAT, PSAT and AP exams. Calculators with computer algebra system (CAS) functionality are not allowed on ACT exams.
If you have additions to the above article please email: firstname.lastname@example.org.
© Joerg Woerner, July 29, 2020. No reprints without written permission.