DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Texas Instruments TI-Nspire CM (Chinese Language - Engineering Validation Tests 1)
| Date of introduction: | Never | Display technology: | LCD dot matrix 16-bit color, backlit |
| New price: | Display size: | 240 * 320 pixels | |
| Size: | 7.5" x 3.4" x 0.65" 190 x 87 x 16 mm3 |
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| Weight: | 8.5 ounces, 204 grams | Serial No: | EVT1-217 |
| Batteries: | 3.7L0800SP Li-Ion | Date of manufacture: | mth 02 year 2011 |
| AC-Adapter: | Origin of manufacture: | China | |
| Precision: | 14 | Integrated circuits: | CPU: ET-LC2010B-0 (T6UJ1XBG-0002) SDRAM and Flash MCP: Samsung K511F57ACC |
| Memories: | |||
| Program steps: | 32M Bytes, 100M Bytes Flash ROM | Courtesy of: | Joerg Woerner |
This
TI-Nspire CM (Chinese Language) with the serial number EVT1-217 was used for
Engineering Validation Tests (EVT - learn more about the
Five Engineering Stages) of the later
TI-Nspire CM-C.
Dismantling
this TI-Nspire CM EVT1 manufactured already in February 2011 by Inventec Corporation in its Pudong Campus in
Shanghai, China reveals a design similar to the original
TI-Nspire CX centered
around a tiny System-on-Chip. Learn more about the Hardware Architecture of TI’s Graphing Calculators
Processor:
The ARM9 CPU is integrated into an ASIC with the markings ET-LC2010B-0 (T6UJ1XBG-0002), obviously from Toshiba, Japan. The ARM9 core is clocked with
132 MHz compared to the 90 MHz of the previous TI-Nspire. Learn more about the Hardware Architecture of TI’s Graphing Calculators.
Based on observations from the original TI-Nspire and the recently discovered
Revision W (NSC CR IV), we assume that the ASIC incorporates a ROM with a
capacity of 128k Bytes used for the first-stage bootloader ("Boot 1")
and a SRAM with a capacity of 128k Bytes.
Memory:
Both the NAND Flash-ROM and the SDRAM with are integrated into a Multichip Package with the part designation Samsung
K511F57ACC-B075. Deciphering the part number reveals the capacity of the
Flash-ROM (128M Bytes) and SDRAM (16M x 16 bits):
| • Product Family K5 = Samsung MCP (2 chips) • Device Type 1 = NAND Flash Rom + Mobile SDR • NAND Flash Density, Organization 1F = 1 Gbit, x8 • RAM Density, Organization 57 = 256 Mbit, x16 • Operating Voltage A = 1.8V NAND, 1.8V DRAM • Flash Block Architecture C = Uniform block • Version C = 4th Generation • Package Type B = FBGA • NAND Flash Speed 0 = None • RAM Speed 75 = 7.5 ns (133MHz@CL3) |
• TI-Nspire CM EVT1
