DATAMATH CALCULATOR MUSEUM
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DATAMATH CALCULATOR MUSEUM |
Texas Instruments TI-Nspire KBD EZ-Spot
| Date of introduction: | July 2007 | Display technology: | LCD dot matrix 16-level greyscale |
| New price: | Display size: | 240 * 320 pixels | |
| Size: | 7.8" x 3.9" x 0.85" | ||
| Weight: | 9.9 ounces | Serial No: | 2016076608 (Base Unit) 2011057389 (Alpha KBD) |
| Batteries: | 4*AAA | Date of manufacture: | mth 05 year 2007 |
| AC-Adapter: | Origin of manufacture: | China (S) | |
| Precision: | 14 | Integrated circuits: | CPU: TI-NS2006A (L9A0702) SDRAM: HYB18L256160 Flash: SST 39WF400A, ST NAND256R3A2BZA6 |
| Memories: | |||
| Program steps: | 20M Bytes, 16M Bytes Flash-ROM | Courtesy of: | Joerg Woerner |
To
reduce theft of this new school-owned TI-Nspire calculator, Texas Instruments
introduced in 2007 the EZ-Spot Teacher Packs with a bright, easy-to-spot,
"school bus yellow" back cover and slide case.
In addition, each unit's faceplate is inscribed with the
words, "SCHOOL PROPERTY."
Dismantling this TI-Nspire KBD EZ-Spot reveals
no surprises, it is identical with a TI-Nspire manufactured in the same month.
Architecture:
Dismantling the TI-Nspire reveals a modern
architecture based on the ZEVIO architecture introduced by LSI Logic early in
2006. The ZEVIO architecture is ideally suited for consumer electronics products
such as GPS navigation systems, electronic toys and edutainment applications,
personal media players, and handheld products. The System-on-Chip (SoC) approach
of the ZEVIO is centered around Intellectual Property blocks from ARM (e.g. the
90 MHz ARM9 32-bit RISC processor), LSI Logic's 200-MHz 16-bit ZSP-400 Digital
Signal Processor, 16-bit SDRAM memory controller, NAND flash memory controller,
USB-2.0 (including USB On the Go), IEEE 1394 Firewire, and Secure Digital I/O
and a LCD controller for TFT displays. We noticed this approach already with the
PLT-SHH1 prototype based on the sophisticated POMAP1509E, a design based on the OMAP™1510 series dual-core processor.
Processor:
The current
(May 2007) chips with the TI-NS2006A-0 / L9A0702 identification are designed in a 0.13um process and manufactured in
any of LSI Logic's foundries, which include Semiconductor Manufacturing
International, Taiwan Semiconductor Manufacturing and United Microelectronics.
Memory:
The TI-Nspire makes use of three different memory chips:
 | NOR Flash-ROM |
| NAND Flash-ROM |
| SDRAM |
Flash memory is non-volatile and does not need a battery to maintain the
information stored in the chip. In the past years two different technologies
emerged in parallel with some advantages and disadvantages.
The NOR Flash-ROM was invented by Toshiba in 1984 and found its way
immediately as a replacement of the more expensive ROM (NRE mask costs) and
EEPROM (device costs) memory. The NOR Flash-ROM's use an address and data bus
to allow the random access to any memory location. Main disadvantages of the NOR
Flash-ROM compared to the NAND Flash-ROM are the higher costs, larger housings
and slower write speeds.
The disassembled TI-Nspire (Manufactured May 2007) makes use of one SST 39WF400A, manufactured by Silicon Storage Technology, Inc. with a a 256k*16 organization. Please keep in mind that even the TI-89 Titanium used 2M*16 Flash-ROM.
The NAND Flash-ROM architecture was introduced by Toshiba in 1989 and is based on pages of typically 512 to 2048 Bytes and blocks of typical 32 or 64 pages.
While programming is performed on a page basis, erasure can only be performed on a block basis. NAND Flash-ROM's requires bad block management to be performed by device driver software or hardware. Due to the missing address bus the NAND Flash-ROM chip doesn't allow random access to the individual memory positions and therefore it can't be used for program memory of a microprocessor. Typical use of the NAND Flash-ROM memory is file based mass-memory storage such as memory cards.
The disassembled TI-Nspire makes use of one ST NAND256R3A2BZA6 NAND Flash-ROM with 32M Bytes size compared with 8M Bytes CMOS NAND EEPROM located in the PLT-SHH1 prototype.
SDRAM is the abbreviation of synchronous dynamic random access memory and is used as program and data memory for microprocessor systems. Each bit of data in a SDRAM is stored in separate condensator on the integrated circuit. Since these capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically.
Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows SDRAM to reach very high density at low cost. Since SDRAM loses its data when the power supply is removed, it is accompanied usually by a NOR Flash memory.
During power-up of the system the program content of the NOR Flash is simply copied into the SDRAM and executed from there. We assume that the TI-Nspire uses the SDRAM as workspace for user data but stores changes on them into the NAND Flash memory.
The disassembled TI-Nspire makes use of one Qimonda HYB18L256160 SDRAM with 16M*16 size compared with 8M*16 SDRAM located in the PLT-SHH1 prototype.
Display:
The TI-Nspire uses a high-contrast display with a
resolution of 240 * 320 pixels, a huge improvement over the TI-89 Titanium with
100 * 160 pixels or the Voyage 200 with 128 * 240 pixels. The large 16-level
greyscale display includes a novel split screen capability with up to 4 views.
ROM-Versions:
| TI-Nspire |
